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gnucap:user:gnucap_verilog_reconciled [2018/05/22 06:38] felixs add verilog preprocessing |
gnucap:user:gnucap_verilog_reconciled [2018/06/05 01:34] (current) felixs s/github/gitlab/ |
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Verilog defines preprocessor macros, such as constants and conditional blocks. | Verilog defines preprocessor macros, such as constants and conditional blocks. | ||
- | Preliminary basic support for `include, `(un)def, `if(n)def, `elsif is implemented as part of https://github.com/gnucap/gnucap-main. This should be sufficient for the netlist/schematic representaion outlined in http://gnucap.org/dokuwiki/doku.php/gnucap:user:netlist_import_and_export | + | Preliminary basic support for `include, `(un)def, `if(n)def, `elsif is implemented as part of https://gitlab.com/gnucap/gnucap-main. This should be sufficient for the netlist/schematic representaion outlined in http://gnucap.org/dokuwiki/doku.php/gnucap:user:netlist_import_and_export |