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gnucap:projects [2025/11/25 06:10] felixs [Device interface wrappers] link to FAQ & resource page |
gnucap:projects [2026/05/05 02:44] (current) felixs update. add schematic editors section |
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| * Simulator netlist formats: Qucsator, ADS, VHDL | * Simulator netlist formats: Qucsator, ADS, VHDL | ||
| * Simulator non-netlist formats: Touchstone | * Simulator non-netlist formats: Touchstone | ||
| - | * Free schematic formats: gEDA/gschem, Kicad/eeschema, Qucs/GUI | + | * Free schematic formats: gEDA/gschem/xschem, Kicad/eeschema, Qucs/GUI |
| * Free PCB layout formats: gEDA/PCB, Kicad/pcbnew | * Free PCB layout formats: gEDA/PCB, Kicad/pcbnew | ||
| * Proprietary PCB/schematic formats: Eagle, Multisim, Orcad | * Proprietary PCB/schematic formats: Eagle, Multisim, Orcad | ||
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| - NGspice rawfile | - NGspice rawfile | ||
| - HDF5 | - HDF5 | ||
| + | - VCD | ||
| + | |||
| + | A promising direction to explore are the (standard compliant) file I/O functions by Modelgen-Verilog. Creating output plugins based on these amounts to implementing the devices and identify/fill gaps in the framework. Complementary VCD output functions should be implemented following the standard. | ||
| One of these is a full summer-of-code project. | One of these is a full summer-of-code project. | ||
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| To qualify for one of these projects, you should first be familiar the target format, at least one application that uses it, and gnucap output code. | To qualify for one of these projects, you should first be familiar the target format, at least one application that uses it, and gnucap output code. | ||
| + | ===== Schematic Editor ===== | ||
| + | |||
| + | Despite its usefulness, Verilog is poorly supported by (free) schematic editors. We could use a schematic editor that can read and write Verilog, preferably with [[gnucap:user:netlist_import_and_export|Verillg-S]] extensions. | ||
| + | Such an editor does not have to be part of Gnucap, but a rewrite from scratch would ideally build on the Gnucap data structures and library. | ||
| + | Existing projects that could use an enhancement for mutual benefit are | ||
| + | |||
| + | 1. gEDA (now lepton). Ships schematic editor. Defines a file format we understand (c.f "gnucap-geda"). Has shown interest in supporting Verilog-S directly, but no developer working on it. The translation of relevant gEDA objects to Verilog-S is documented. | ||
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| + | 2. QUCS has experimental native support for Verilog-S in development. Lacks features and needs work. Potential for nicely interactive simulation in the long run. | ||
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| + | 3. xschem. Heavily used by "IHP-OpenPDK" users, but lacks data exchange. Provides Verilog-ish export but no Verilog-S and no import. The file format ought to be similar to gEDA, yet the translation to Verilog-S is not documented. | ||