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gnucap:projects:nlnet:verilogams [2023/11/02 15:16] felixs 20231031 |
gnucap:projects:nlnet:verilogams [2023/11/03 01:36] (current) aldavis |
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| The code is available [[http://git.savannah.gnu.org/cgit/gnucap/gnucap-modelgen-verilog.git/commit/?h=pp&id=b264644b653495fc8bdbe1c5402ef2a06fd7e1b8|here]] and combines preprocessing with evaluating derivatives (Task 1b). | The code is available [[http://git.savannah.gnu.org/cgit/gnucap/gnucap-modelgen-verilog.git/commit/?h=pp&id=b264644b653495fc8bdbe1c5402ef2a06fd7e1b8|here]] and combines preprocessing with evaluating derivatives (Task 1b). | ||
| == c) Add support for "attribute instance". == | == c) Add support for "attribute instance". == | ||
| + | Attributes are the little bits of info that are important in a different context, like schematics and PC boards. Verilog gives us a standard way to do this. It's now implemented in lang_verilog. It's in the snapshot, and in the "attributes-5" branch. [[https://git.savannah.gnu.org/cgit/gnucap.git/log/?h=attributes-5|here]]. There is technical documentation [[gnucap:manual:tech:plugins:languages:attributes|here]] and user documentation for its use in Verilog [[gnucap:manual:languages:verilog|here]]. | ||
| == d) Provide logic gates as plug-ins, accessible from Verilog netlists. == | == d) Provide logic gates as plug-ins, accessible from Verilog netlists. == | ||
| == e) Integrate "model card" hierarchy into Verilog language semantics. == | == e) Integrate "model card" hierarchy into Verilog language semantics. == | ||