Make a connection between a port and the rest of the circuit, by name as in Verilog. Usually this is not needed because the inherited method will do the right thing, which is to look up the index then do set_port_by_index.
Make a connection between a port and the rest of the circuit, by position as in Spice. Usually (for node_t based ports, the usual voltage or logic ports) this is not needed because the inherited method will do the right thing. For ports that are not based on node_t, such as current ports in Spice, this function may be needed.
Return the name of a port given its index. This is required, because all devices have unique port names.